CV

UKRI Funded PhD in Neural Network Acceleration

Imperial College London

Integrated Masters in Electronic and Information Engineering

Imperial College London

• Key Machine Learning and Mathematics modules
  • Deep Learning (88%)
  • Advanced Deep Learning Systems (81%)
  • Mathematics for Machine Learning (84%)
  • Computer Vision (78%)
  • Digital Signal Processing (82%)
  • Signal Processing and Machine Learning for Finance (84%)
  • Probability and Stochastic Processes (77%)
  • Topics in Large Dimensional Data Processing (77%)
  • Operations Research (76%)
• Key Hardware and Software Engineering modules
  • Digital System Design (84%)
  • Advanced Computer Architecture (75%)
  • Introduction to Machine Learning (76%)
  • Embedded Systems (72%)
  • Instruction Architectures and Compilers (70%)

GPU Design Verification engineer

Apple GPU

• Using SystemVerilog and UVM, I work to verify part of a complex GPU frontend design.
  • This role was a continuation from my internship. My key responsibilites include - Owning testbenches for multiple units. - Understanding complicated micro-architectural features functionally. - Verifying the design against the architectural specification and thinking beyond the specification to identify bugs. - Developing robust testbenches and stimulus which are maintainable and scalable across multiple generations.

GPU Design Verification Intern

Apple GPU

• Using SystemVerilog and UVM, I worked as part of a small team working on verification of a high performance interconnect network.
  • Designed stimulus
  • Improved testbenches
  • Improved performance of testbenches
  • Developed models based upon architectural specification
  • Debugged failures using logs and waveform viewers
  • Developed scripts to automate tasks
  • Developed verification tools to aid in debugging

Logical Design Intern

Graphcore

• Design, verification, and build of multiple modules in SystemVerilog with the use of C++ and Python for infrastructure.
  • Used SystemVerilog and EDA tools to design, synthesize and verify different Floating Point arithmetic unit hardware modules.
  • Developed these designs using various optimization techniques in order to meet tight requirements by analyzing timing and area reports.
  • Optimised designs using physical synthesis tools.
  • Created custom testbenches to verify the designs using SystemVerilog.

Master's Project - Learnable quantisation through paramaterised companding functions.

• Through learnable quantisation, I was able to halve the area footprint of LUT-based neural networks whilst improving network accuracy. I developed a novel way to train a non-standard data representation through backpropgation of the network loss. This allowed layers to use non-standard data formats which were directly optimised for the task, resulting in lower area and power consumption.

Hardware-based mixed-format arithmetic accelerator

• Designed an arithmetic accelerator deployed on an FPGA to accelerate computations written in C. This was an exploratory project in which the designs were iterated and optimised for timing and area. The final design incorporated DMA accesses and a custom hardware block including a CORDIC implementation.

ProPutter

• Built an embedded system deployed on a microprocessor which, when mounted on a golf putter, would take measurements of the user's putt, and provide feedback on the user's performance via a web-app. This project involved optimising the design for latency and memory usage.

Synth-Starter

• Built an embedded system deployed on a real-time operating system, which collated information from multiple nodes in a wired network and distributed commands to enable the nodes to play music in sync. This project involved developing custom protocols for communication between nodes and optimising said protocols for latency and bandwidth. I explored thread-safe design practices and how to manage a distributed system with hardware constraints.

Mars Rover

• Designed an image processing accelerator to be deployed on an FPGA. This included hardware implementations of filtering, color space conversions and gradient detection.

Custom multi-core CPU

• Designed a custom pipelined dual core CPU with arbitration logic and floating point capabilities. This project involved designing a custom ISA and Pipeline. I explored the design of a pipelined CPU, and the challenges of designing a CPU with multiple cores.